|AND gate||Tập tin:AndGate.gif|
|NAND (not and) gate||Tập tin:Nand.gif|
|NOR (not or) gate||Tập tin:Nor.gif|
|NOT gate (inverter)||Tập tin:Not.gif|
|XOR (exclusive or) gate|
|XNOR (exclusive nor) gate|
A Flip-flop is an example of a bistable multivibrator, that is a device with two stable states. These states are, of course, 0 or 1 (low or high). A flip-flop is a memory device, and thus will store a value while power remains in the circuit. It is also sometime referred to as a latch, because of its ability to 'latch' onto data.
There are several different types of flip-flop each with its own uses and peculiarities. The 4 main types of flip flop are : SR, JK, D, and T and each will be dicussed in more detail.
An SR (Set/Reset) Flip-flop, is an asychronous device, that is, it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR flip-flop can be created with two NOR gates that have a cross-feedback loop.
In practise, an SR flip-flop will have two complementary outputs, Q and inverse Q. For this reason any state of S and R is deemed to be an invalid state for an SR flip-flop.
When a high is applied to the Set line of an SR flip-flop, the Q output is latched high (and Q' low). Thus once the set line returns to low, the Q output will still remain high, this is how the flip-flop serves as a memory device. Conversely, a high input on the Reset line will drive the Q output low (and Q' high), effectively resetting the flip-flop('memory').
As you can see we have an invalid state, that is when both the S and R lines are high, the output is low on both Q and Q' lines. When both the S and R lines are held low, the output is the latched state, that is, it 'remembers' what was on the lines prior to them being driven low.
Some of you may have noticed that when the circuit is first switched on, both outputs will revert to low(0) which would seem to indicate an invalid start up condition. It turns out that this is actually true, however, the invalid condition is unstable with S and R lines low leading the circuit to stabilise, into either the set or reset condition, quickly. This is the result of the NOR gates being used and the manufacturing process used to create them. Suffice to say one gate will usually react quicker thus stabilising the circuit. This is called a race condition and realistically always resolves into a stable state quite quickly.
Gated SR Flip-flop[sửa]
In some situations it may be desirable to dictate when the flip-flop can and cannot latch. This is a simple extension of the SR flip-flop which basically provides an enable line which must be driven high before data can be latched. Since a control line is now required, the Gated SR flip-flop is a synchronous device.
As you can deduce from the circuit diagram, when the enable input is low, then the outputs from the AND gates must also be low, thus the Q and Q' outputs remain latched to the previous data. Thus only when the enable input is high can the state of the flip-flop change, as shown in the truth table.
The D flip-flop is a simple extension of the gated SR flip-flop that removes the posibility of invalid output states.
Since the gated SR flip-flop allows us to latch the outputs without regard for the status inputs, we can remove one of the inputs by driving both the Set and Reset inputs with a complementary driver. Simply, we remove one input and automatically make it the inverse of the remaining input.
The JK flip-flop is a simple enhancement of the SR flip-flop where the state J=K=1 is not forbidden. It works just like a SR FF where J is serving as set input and K serving as reset. The only difference is that for the formerly “forbidden” combination J=K=1 this flip-flop now performs an action: it inverts its state. As the behavior of the JK flip-flop is completely predictable under all conditions, this is the preferred type of flip-flop for most logic circuit designs.
Trigger Flip-Flops (T Flip-Flops)[sửa]
A T flip-flop is a JK flip-flop with connected inputs. Therefore it can only toggle or preserve its state. A toggle flip-flop only makes sense with a control input, otherwise it would just flip around the whole time and would be a pulse generator – but not a real flip-flop. Note that in a synchronous circuit the T input is connected to the J- and K- Input, thus the T input controls if the FF toggles while the clock determines when the FF toggles. In asynchronous circuits the T input is connected to the clock line of the JK FF and the J and K input are set to 1.Periyadi mone toggles as soon as T is set to 1. Asynchronous Set and Reset