Điện tử/Linh kiện điện tử/Mạch điện tổng hợp bộ sóng 555

Cơ Cấu

Pinout diagram

The connection of the pins is as follows:

Pin	Name	Purpose
1	GND	Ground, low level (0 V)
2	TRIG	OUT rises, and interval starts, when this input falls below 1/3 VCC.
3	OUT	This output is driven to +VCC or GND.
4	Bản mẫu:Overline	A timing interval may be interrupted by driving this input to GND.
5	CTRL	"Control" access to the internal voltage divider (by default, 2/3 VCC).
6	THR	The interval ends when the voltage at THR is greater than at CTRL.
7	DIS	Open collector output; may discharge a capacitor between intervals.
8	V+, VCC	Positive supply voltage is usually between 3 and 15 V.

Cấu Trúc

Lối Hoạt Động

Một Trạng Thái Ổn

Schematic of a 555 in monostable mode

The relationships of the trigger signal, the voltage on C and the pulse width in monostable mode

In the monostable mode, the 555 timer acts as a “one-shot” pulse generator. The pulse begins when the 555 timer receives a signal at the trigger input that falls below a third of the voltage supply. The width of the output pulse is determined by the time constant of an RC network, which consists of a capacitor (C) and a resistor (R). The output pulse ends when the charge on the C equals 2/3 of the supply voltage. The output pulse width can be lengthened or shortened to the need of the specific application by adjusting the values of R and C.

The output pulse width of time t, which is the time it takes to charge C to 2/3 of the supply voltage, is given by

$t = RC\ln(3) \approx 1.1 RC$

where t is in seconds, R is in ohms and C is in farads. See RC circuit for an explanation of this effect.

Astable mode

Standard 555 Astable Circuit

In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having a specified frequency. Resistor R₁ is connected between V_CC and the discharge pin (pin 7) and another resistor (R₂) is connected between the discharge pin (pin 7), and the trigger (pin 2) and threshold (pin 6) pins that share a common node. Hence the capacitor is charged through R₁ and R₂, and discharged only through R₂, since pin 7 has low impedance to ground during output low intervals of the cycle, therefore discharging the capacitor.

In the astable mode, the frequency of the pulse stream depends on the values of R₁, R₂ and C:

$f = \frac{1}{\ln(2) \cdot C \cdot (R_1 + 2R_2)}$

The high time from each pulse is given by

$\mathrm{high} = \ln(2) \cdot (R_1 + R_2) \cdot C$

and the low time from each pulse is given by

$\mathrm{low} = \ln(2) \cdot R_2 \cdot C$

where R₁ and R₂ are the values of the resistors in ohms and C is the value of the capacitor in farads.
note: power of R₁ must be greater than $\frac{V_{cc}^{2}}{R_1}$

To achieve a duty cycle of less than 50% a diode can be added in parallel with R₂ towards the capacitor. This bypasses R₂ during the high part of the cycle so that the high interval depends only on R₁ and C.

Tham Khảo

• 555_timer_IC